Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop

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Yadu Prasad Gyawali
Mohit Angurala

Abstract

This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements.

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How to Cite
Gyawali, Y. P. ., & Angurala, M. . (2022). Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop. International Journal on Future Revolution in Computer Science &Amp; Communication Engineering, 8(1), 27–31. Retrieved from http://ijfrcsce.org/index.php/ijfrcsce/article/view/2103
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