An Effective Low Power Ring Oscillator Based All Digital Phase Locked Loop

Abstract

The All digital phase-locked loops (ADPLL) widely employed in the data communication systems including, but not limited to, the implementation of the frequency multiplication and clock synchronization circuits. A phase-interpolator is utilized for power consumption reduction by using TDC in a ring-oscillator in a fractional-N phase-locked loop. A predicted-phase-interpolation method is used to calculate the integer and fractional parts of the frequency-division-ratio and to find two interpolation clocks. The prediction method gives a significant power reduction in the proposed PIFC by enabling the use of low-frequency clocks for phase interpolation